Backside illuminated image sensor with shallow backside trench for photodiode isolation

ABSTRACT

A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer, and the resulting structure provides reductions in carrier recombination and crosstalk between adjacent photosensitive elements. The image sensor may be implemented in a digital camera or other type of digital imaging device.

CROSS REFERENCE TO RELATED APPLICATIONS

The present invention is related to the inventions described incommonly-assigned U.S. Patent Applications Kodak Docket No. 94870,entitled “Color Filter Array Alignment Mark Formation in BacksideIlluminated Image Sensors,” Kodak Docket No. 94872, entitled “WaferLevel Processing for Backside Illuminated Image Sensors,” and KodakDocket No. 94889, entitled “Backside Illuminated Image Sensor withReduced Dark Current,” which are concurrently filed herewith. Thedisclosures of these related applications are incorporated by referenceherein in their entirety.

FIELD OF THE INVENTION

The present invention relates generally to electronic image sensors foruse in digital cameras and other types of imaging devices, and moreparticularly to processing techniques for use in forming backsideilluminated image sensors.

BACKGROUND OF THE INVENTION

A typical electronic image sensor comprises a number of light sensitivepicture elements (“pixels”) arranged in a two-dimensional array. Such animage sensor may be configured to produce a color image by forming anappropriate color filter array (CFA) over the pixels. Examples of imagesensors of this type are disclosed in U.S. Patent ApplicationPublication No. 2007/0024931, entitled “Image Sensor with Improved LightSensitivity,” which is incorporated by reference herein.

As is well known, an image sensor may be implemented using complementarymetal-oxide-semiconductor (CMOS) circuitry. In such an arrangement, eachpixel typically comprises a photodiode and other circuitry elements thatare formed in a silicon sensor layer on a silicon substrate. One or moredielectric layers are usually formed above the silicon sensor layer andmay incorporate additional circuitry elements as well as multiple levelsof metallization used to form interconnects. The side of the imagesensor on which the dielectric layers and associated levels ofmetallization are formed is commonly referred to as the frontside, whilethe side having the silicon substrate is referred to as the backside.

In a frontside illuminated image sensor, light from a subject scene isincident on the frontside of the image sensor, and the silicon substrateis relatively thick. However, the presence of metallization levelinterconnects and various other features associated with the dielectriclayers on the frontside of the image sensor can adversely impact thefill factor and quantum efficiency of the image sensor.

A backside illuminated image sensor addresses the fill factor andquantum efficiency issues associated with the frontside dielectriclayers by thinning or removing the thick silicon substrate and arrangingthe image sensor such that light from a subject scene is incident on thebackside of the image sensor. Thus, the incident light is no longerimpacted by metallization level interconnects and other features of thedielectric layers, and fill factor and quantum efficiency are improved.

However, in many backside illuminated image sensors, charge storageregions associated with the sensor photodiodes are located a substantialdistance away from the backside surface. This is problematic in thatmany carriers generated by the photodiodes from incident light are lostbefore they can be collected, for example, due to recombination withother carriers or crosstalk between adjacent photodiodes.

Accordingly, a need exists for an improved backside illuminated imagesensor which does not suffer from the excessive carrier loss problemdescribed above.

SUMMARY OF THE INVENTION

Illustrative embodiments of the invention provide backside illuminatedimage sensors having reduced carrier recombination and crosstalk, andthus improved performance.

In accordance with one aspect of the invention, a process of forming abackside illuminated image sensor is provided. The process is a waferlevel process for forming a plurality of image sensors each having apixel array configured for backside illumination, with the image sensorsbeing formed utilizing an image sensor wafer. The image sensor wafercomprises a substrate and a sensor layer formed over the substrate. Theprocess includes the steps of forming backside trenches in a backsidesurface of the sensor layer, implanting a dopant into the sensor layerthrough the backside trenches so as to form backside field isolationimplant regions corresponding to the backside trenches, filling thebackside trenches, forming at least one antireflective layer over thefilled backside trenches, and further processing the image sensor waferto form the plurality of image sensors.

The image sensor wafer may be, for example, a silicon-on-insulator (SOI)wafer having a buried oxide layer arranged between the substrate and thesensor layer, or an epitaxial wafer having a P− sensor layer formed overa P+ substrate.

Prior to forming the backside trenches, a pad oxide layer may be formedover the sensor layer, and a pad nitride layer may be formed over thepad oxide layer. Alignment marks may then be formed that extend throughthe oxide and nitride layers and into the sensor layer. The backsidetrenches may be etched through the nitride and oxide layers, and a lineroxide layer may be formed within the backside trenches. The backsidetrenches may then be filled with a material such as oxide orpolysilicon.

The antireflective layer may comprise an antireflective oxide layerformed on the backside surface of the sensor layer, and anantireflective nitride layer formed over the antireflective oxide layer.Prior to or after forming the antireflective oxide layer, a backsidepassivation implant operation may be performed.

The process may further include a backside well isolation implantoperation. This may involve, for example, depositing a photoresist overthe antireflective layer, patterning the photoresist to form openingsover the backside trenches, and implanting a dopant through the openingsto form backside well isolation implant regions corresponding to thebackside trenches.

In one of the illustrative embodiments, the step of further processingthe image sensor wafer to form the plurality of image sensors furthercomprises the steps of forming an oxide layer over the antireflectivelayer, attaching a temporary carrier wafer to a backside surface of theoxide layer, removing the substrate, forming photosensitive elements ofthe pixel arrays in the sensor layer, forming frontside trenches in afrontside surface of the sensor layer, forming frontside field isolationimplant regions corresponding to the frontside trenches, filling thefrontside trenches, forming frontside well isolation implant regionscorresponding to the frontside trenches, forming at least one dielectriclayer on the frontside surface of the sensor layer, attaching a handlewafer to a frontside surface of said at least one dielectric layer,removing the temporary carrier wafer, and separating the image sensorwafer into the plurality of image sensors.

In accordance with another aspect of the invention, a backsideilluminated image sensor comprises a sensor layer implementing aplurality of photosensitive elements of a pixel array, an oxide layeradjacent a backside surface of the sensor layer, and at least onedielectric layer adjacent a frontside surface of the sensor layer. Thesensor layer further comprises a plurality of backside trenches formedin the backside surface of the sensor layer and arranged to provideisolation between respective pairs of the photosensitive elements. Thebackside trenches have corresponding backside field isolation implantregions formed in the sensor layer.

A backside illuminated image sensor in accordance with the invention maybe advantageously implemented in a digital camera or other type ofimaging device, and provides improved performance in such a devicewithout significantly increasing image sensor die size or cost.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features, and advantages of the presentinvention will become more apparent when taken in conjunction with thefollowing description and drawings wherein identical reference numeralshave been used, where possible, to designate identical features that arecommon to the figures, and wherein:

FIG. 1 is a block diagram of a digital camera having a backsideilluminated image sensor configured in accordance with an illustrativeembodiment of the invention;

FIGS. 2 through 14 are cross-sectional views showing portions of abackside illuminated image sensor at various steps in an exemplaryprocess for forming such an image sensor, in accordance with anillustrative embodiment of the invention; and

FIG. 15 is a plan view of an image sensor wafer comprising multipleimage sensors formed using the exemplary process of FIGS. 2 through 14.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be illustrated herein in conjunction withparticular embodiments of digital cameras, backside illuminated imagesensors, and processing techniques for forming such image sensors. Itshould be understood, however, that these illustrative arrangements arepresented by way of example only, and should not be viewed as limitingthe scope of the invention in any way. Those skilled in the art willrecognize that the disclosed arrangements can be adapted in astraightforward manner for use with a wide variety of other types ofimaging devices and image sensors.

FIG. 1 shows a digital camera 10 in an illustrative embodiment of theinvention. In the digital camera, light from a subject scene is input toan imaging stage 12. The imaging stage may comprise conventionalelements such as a lens, a neutral density filter, an iris and ashutter. The light is focused by the imaging stage 12 to form an imageon an image sensor 14, which converts the incident light to electricalsignals. The digital camera 10 further includes a processor 16, a memory18, a display 20, and one or more additional input/output (I/O) elements22.

Although shown as separate elements in the embodiment of FIG. 1, theimaging stage 12 may be integrated with the image sensor 14, andpossibly one or more additional elements of the digital camera 10, toform a compact camera module.

The image sensor 14 is assumed in the present embodiment to be a CMOSimage sensor, although other types of image sensors may be used inimplementing the invention. More particularly, the image sensor 14comprises a backside illuminated image sensor that is formed in a mannerto be described below in conjunction with FIGS. 2 through 14. The imagesensor generally comprises a pixel array having a plurality of pixelsarranged in rows and columns and may include additional circuitryassociated with sampling and readout of the pixel array, such as signalgeneration circuitry, signal processing circuitry, row and columnselection circuitry, etc. This sampling and readout circuitry maycomprise, for example, an analog signal processor for processing analogsignals read out from the pixel array and an analog-to-digital converterfor converting such signals to a digital form. These and other types ofcircuitry suitable for use in the digital camera 10 are well known tothose skilled in the art and will therefore not be described in detailherein. Portions of the sampling and readout circuitry may be arrangedexternal to the image sensor, or formed integrally with the pixel array,for example, on a common integrated circuit with photodiodes and otherelements of the pixel array.

The image sensor 14 will typically be implemented as a color imagesensor having an associated CFA pattern. Examples of CFA patterns thatmay be used with the image sensor 14 include those described in theabove-cited U.S. Patent Application Publication No. 2007/0024931,although other CFA patterns may be used in other embodiments of theinvention. As another example, a conventional Bayer pattern may be used,as disclosed in U.S. Pat. No. 3,971,065, entitled “Color Imaging Array,”which is incorporated by reference herein.

The processor 16 may comprise, for example, a microprocessor, a centralprocessing unit (CPU), an application-specific integrated circuit(ASIC), a digital signal processor (DSP), or other processing device, orcombinations of multiple such devices. Various elements of the imagingstage 12 and the image sensor 14 may be controlled by timing signals orother signals supplied from the processor 16.

The memory 18 may comprise any type of memory, such as, for example,random access memory (RAM), read-only memory (ROM), Flash memory,disk-based memory, removable memory, or other types of storage elements,in any combination.

Functionality associated with sampling and readout of the pixel arrayand the processing of corresponding image data may be implemented atleast in part in the form of software that is stored in memory 18 andexecuted by processor 16.

A given image captured by the image sensor 14 may be stored by theprocessor 16 in memory 18 and presented on display 20. The display 20 istypically an active matrix color liquid crystal display (LCD), althoughother types of displays may be used. The additional I/O elements 22 maycomprise, for example, various on-screen controls, buttons or other userinterfaces, network interfaces, memory card interfaces, etc.

Additional details regarding the operation of a digital camera of thetype shown in FIG. 1 can be found, for example, in the above-cited U.S.Patent Application Publication No. 2007/0024931.

It is to be appreciated that the digital camera as shown in FIG. 1 maycomprise additional or alternative elements of a type known to thoseskilled in the art. Elements not specifically shown or described hereinmay be selected from those known in the art. As noted previously, thepresent invention may be implemented in a wide variety of other types ofdigital cameras or imaging devices. Also, as mentioned above, certainaspects of the embodiments described herein may be implemented at leastin part in the form of software executed by one or more processingelements of an imaging device. Such software can be implemented in astraightforward manner given the teachings provided herein, as will beappreciated by those skilled in the art.

The image sensor 14 may be fabricated on a silicon substrate or othertype of substrate. In a typical CMOS image sensor, each pixel of thepixel array includes a photodiode and associated circuitry for measuringthe light level at that pixel. Such circuitry may comprise, for example,transfer gates, reset transistors, select transistors, outputtransistors, and other elements, configured in a well-known conventionalmanner.

As indicated previously, an excessive carrier loss problem can arise inconventional backside illuminated image sensors, due to carrierrecombination prior to collection as well as crosstalk between adjacentphotodiodes. One possible approach to addressing this problem is toutilize a low-doped epitaxial layer for the sensor layer in which thephotodiodes are formed, so as to extend the depletion regions associatedwith the respective photodiodes and thereby reduce carrierrecombination. However, we have discovered that such an approach canlead to increased “dark” current and degradations in quantum efficiency.Techniques for addressing the carrier loss problem without increasingdark current or degrading quantum efficiency will now be described withreference to FIGS. 2 through 14. It should be noted that thecross-sectional views shown in these figures are simplified in order toclearly illustrate various aspects of the present invention, and are notnecessarily drawn to scale. A given embodiment may include a variety ofother features or elements that are not explicitly illustrated but wouldbe familiar to one skilled in the art as being commonly associated withimage sensors of the general type described.

The techniques illustrated in FIGS. 2 through 14 generally involveprocessing an image sensor wafer to form a plurality of image sensorseach having a pixel array configured for backside illumination. Each ofFIGS. 2 through 8 will show various process steps as applied to twoseparate image sensor wafers, one a silicon-on-insulator (SO) wafer 200and the other an epitaxial wafer 210. After completion of the processsteps illustrated in FIG. 8, the resulting image sensor wafers have atthat point have substantially the same structure. Thus, FIGS. 9 through14 will show the remaining process steps as applied to only a singleimage sensor wafer. Although the SO and epitaxial wafers 200 and 210will be used to illustrate the invention, it is to be appreciated thatother types of wafers may be used.

The portions of the image sensor wafers 200 and 210 as shown in FIG. 2generally correspond to a particular one of the image sensors, and maybe viewed as including a pixel array area surrounded by periphery areas.The periphery areas may include or be associated with bond pad areas, orother portions of the image sensor.

The image sensor wafer 200 or 210 also has a frontside and a backside.With reference to FIG. 2, the backside of these image sensor waferscorresponds generally to the top of the wafers. Thus, in the completedimage sensor wafer shown in FIG. 14, light from a subject scene will beincident on the photodiodes or other photosensitive elements of thepixel array through the side identified in that figure as the backside,which again is the top of the wafer. The terms “frontside” and“backside” will be used herein to denote particular sides of an imagesensor wafer or an image sensor formed from such a wafer, as well assides of particular layers of the image sensor wafer or correspondingimage sensor.

It should be noted that terms such as “on” or “over” when used inconjunction with layers of an image sensor wafer or corresponding imagesensor are intended to be construed broadly, and therefore should not beinterpreted to preclude the presence of one or more intervening layersor other intervening image sensor features or elements. Thus, a givenlayer that is described herein as being formed on or formed over anotherlayer may be separated from the latter layer by one or more additionallayers.

Referring now to FIG. 2, the SOI image sensor wafer 200 comprises asilicon substrate 202, a buried oxide (BOX) layer 204 formed on thesubstrate, and a silicon sensor layer 206 formed on the buried oxidelayer. The epitaxial image sensor wafer 210 comprises a P+ substrate212, and a P− sensor layer 214 formed over the P+ substrate. Asindicated above, various layers of an image sensor wafer may bedescribed herein as having frontside and backside surfaces. For example,the sensor layer 206 has a frontside surface 206F and a backside surface206B.

For the remaining description of FIGS. 2 through 8, the process will bedescribed primarily with reference to the SOI image sensor wafer 200,with the understanding that similar steps are applied to the epitaxialwafer 210, as illustrated in these figures. Similar reference numeralswill be used to denote corresponding elements in the SOI and epitaxialwafers, with those of the latter wafer being distinguished from those ofthe former by a prime symbol (′). Thus, for example, element 220 in theSOI wafer corresponds to element 220 in the epitaxial wafer.

In the steps illustrated in FIG. 2, a pad oxide layer 220 is formed overthe sensor layer 206 of the SOI wafer 200, and a pad nitride layer 222is formed over the pad oxide layer 220. As will be seen, portions ofthese layers in a pixel array area of an image sensor are eventuallyremoved, but other portions are utilized to form, for example, bond padstructures in periphery areas of the image sensor.

As shown in FIG. 3, alignment marks 300 are patterned and formed, whichwill generally involve lithography operations such as photoresistdeposition followed by exposing, developing and etching. The alignmentmarks are patterned in accordance with a desired alignment mark pattern,which will generally depend upon the particular type of lithographyequipment being used to process the image sensor wafer. In this example,the alignment marks 300 extend through the pad oxide and nitride layers220, 222 and sensor layer 206 to an underlying surface of the buriedoxide layer 204. Thus, the alignment marks extend through the entiresensor layer 206. These alignment marks can be used to provide alignmentbetween frontside and backside features, and to align CFA elements andtheir associated microlenses to corresponding photodiodes or otherphotosensitive elements of the pixel array.

The alignment marks 300 may comprise polysilicon. Advantageoustechniques for forming polysilicon alignment marks of this type in abackside illuminated image sensor are disclosed in the above-cited U.S.Patent Application Kodak Docket No. 94870, although a wide variety ofother techniques may be used to form alignment marks 300.

Backside trenches 400 are then formed in the backside surface 206B ofthe sensor layer 206, as illustrated in FIG. 4. A dopant is implantedinto the sensor layer through the backside trenches 400 as indicated bythe downward pointing arrows so as to form backside field isolationimplant regions 402. The backside trenches in this embodiment are formedby etching the trenches through the nitride and oxide layers 222, 220.The trenches in the illustrative embodiment are shallow trenches, andmay have a depth of approximately 0.1 to 0.5 micrometers (μm). Thetrench width is typically about 0.1 to 0.2 μm, but will generally dependon the size of the photodiodes, which may vary from implementation toimplementation. A narrower width is generally preferred in terms ofproviding an improved photoresponse.

The backside trenches 400 and their associated field isolation implantregions 402 serve to dielectrically isolate the backside of each pixelof the pixel array, which results in less carrier recombination andreduced crosstalk in the completed structure shown in FIG. 14.

The backside trenches 400 may be arranged so as to appear as a grid in atop-down plan view of the pixel array area of a given image sensor. Insuch an arrangement, each photodiode may be located in one of the gridpositions so as to be substantially surrounded by backside trenches.

A liner oxide layer may be formed within the backside trenches 400.Typically the liner oxide will have a thickness of about 50 to 150Angstroms. The field isolation implant can be done before or after theformation of the liner oxide layer.

The dopant used for the field isolation implant is an n-type dopant,such as arsenic or phosphorus, if the pixel array is based on p-typemetal-oxide-semiconductor (PMOS) circuitry, while a p-type dopant suchas boron or indium would be used if the pixel array is based on n-typemetal-oxide-semiconductor (NMOS) circuitry. Typical concentration rangesfor the field isolation implant are from about 5×10¹² to 5×10¹³atoms/cm³.

Referring now to FIG. 5, the backside trenches 400 are filled with amaterial 500 and planarized, and the pad oxide and nitride layers 220,222 are removed. The fill material 500 may comprise, for example, oxideor polysilicon. Doped polysilicon can be used to absorb blue lightbetween pixels and further reduce crosstalk. However, the quantumefficiency for the blue light will also be lower when using dopedpolysilicon as a fill material.

Antireflective layers are then formed over the filled backside trenchesof the sensor layer 206, as illustrated in FIG. 6. More particularly, anantireflective oxide layer 600 is formed on the backside surface of thesensor layer, and an antireflective nitride layer 602 is formed over theantireflective oxide layer 600. The antireflective oxide layer has athickness of approximately 50 Angstroms and the antireflective nitridelayer has a thickness of approximately 500 Angstroms, although othervalues can be used. The antireflective oxide and nitride layers help toimprove quantum efficiency.

The downward pointing arrows in FIG. 6 illustrate the performance of abackside passivation implant operation in conjunction with the formationof the antireflective oxide layer 600. This passivation implantoperation may performed before or after the formation of the oxide layer600, and creates a passivation implant region 604 that serves to quenchsurface states at the backside surface of the sensor layer 206.

Like the field isolation implant of FIG. 4, the backside passivationimplant of FIG. 6 will use an n-type dopant for a PMOS pixel array or ap-type dopant for an NMOS pixel array. Also, suitable concentrations forthe passivation implant are the same as those identified above for thefield isolation implant, that is, from about 5×10¹² to 5×10¹³ atoms/cm³.

FIG. 7 illustrates the performance of a backside well isolation implantoperation. Such an operation is considered optional, but can provideadditional lateral isolation between adjacent photodiodes to be formedin the sensor layer 206. In this example, a photoresist 700 is depositedover the antireflective nitride layer 602 and patterned to form openings702 over respective ones of the backside trenches 400. Then, a wellisolation implant operation is performed, as indicated by the downwardpointing arrows, to implant a dopant through the openings 702. Thisoperation forms backside well isolation implant regions 704 associatedwith the respective backside trenches. Forming the regions 704 from thebackside rather than the frontside allows narrower regions to be formed,which can enhance performance.

The dopant used for the well isolation implant, like those used for theother implants previously described, will be an n-type dopant for a PMOSpixel array or a p-type dopant for an NMOS pixel array. Suitableconcentrations for the well isolation implant are from about 5×10¹¹ to5×10¹³ atoms/cm³.

Any remaining portions of the photoresist 700 are then stripped, and anoxide layer 800 is deposited over the antireflective nitride layer 602as illustrated in FIG. 8. The oxide layer 800 may be deposited to athickness of about 0.1 to 0.5 μm. The backside surface of the oxidelayer 800 may then be subject to a chemical-mechanical polishing (CMP)operation to prepare the surface for bonding of a temporary carrierwafer.

FIG. 9 shows the image sensor wafer structure after a temporary carrierwafer 900 is bonded to the backside surface of the oxide layer 800 andthe substrate 202 and buried oxide layer 204 are removed. The substratemay be removed using, for example, grinding, polishing or etchingtechniques, in any combination. For the SOI wafer 200, the substrate 202is removed down to the buried oxide layer 204, and then the buried oxidelayer is removed. For the epitaxial wafer 210, the substrate removalprocess is configured to terminate when the alignment marks 300 arereached. As indicated previously, because the structures formed from theSOI wafer 200 and the epitaxial wafer 210 are at this pointsubstantially the same, the remaining portions of the process will bedescribed with reference to a single image sensor wafer structure. Inthis structure as shown in FIG. 9, the sensor layer 206 or 214 is moreparticularly identified, by way of illustrative example, as a P− sensorlayer.

The backside temporary carrier wafer 900 may comprise, for example, atype of wafer commonly referred to as a handle wafer. The temporarycarrier wafer may be attached to the image sensor wafer using epoxy oranother suitable adhesive.

Although the temporary carrier wafer is shown as a P− wafer in thisembodiment, this is by way of example only, and other types of dopingsmay be used. Also, the sensor layer may use dopings other than thoseillustrated in the figure. For example, the sensor layer as illustratedin FIG. 9 has a P− doping, but the processing operations could bemodified in a straightforward manner to use an alternative doping suchas an N− doping. Other doping indications shown adjacent thecross-sectional views in FIGS. 2 through 14 may be similarly varied inother embodiments, as will be appreciated by those skilled in the art.

FIG. 10 shows the image sensor wafer flipped over for furtherprocessing.

As illustrated in FIG. 11, this further processing generally involvesforming photosensitive elements 1100 of the pixel arrays in the sensorlayer 206 or 214, forming frontside trenches 1102 in a frontside surfaceof the sensor layer, forming frontside field isolation implant regionscorresponding to the frontside trenches, filling the frontside trenches,forming frontside well isolation implant regions 1104 corresponding tothe frontside trenches, and forming a dielectric layer 1106 on thefrontside surface of the sensor layer. As indicated previously herein,the photosensitive elements of the pixel arrays in the illustrativeembodiments comprise photodiodes.

The frontside trenches 1102 and their associated implant regions may beformed using techniques similar to those described above for formationof the backside trenches 400 and their associated implant regions.

The dielectric layer 1106 in this embodiment comprises multiple layersof dielectric material and may include, for example, an interlayerdielectric (ILD) and an intermetal dielectric (IMD) that separatesmultiple levels of metallization. Various image sensor features such asinterconnects, gates or other circuitry elements may be formed withinthe dielectric layer 1106 using conventional techniques. Although only asingle dielectric layer 1106 is shown in the diagram of FIG. 1, otherembodiments may comprise multiple dielectric layers, possibly separatedfrom one another by one or more intervening layers. Metal conductors1108 formed on a frontside surface of the dielectric layer 1106represent the last metal layer in the image sensor wafer.

An oxide layer 1200 is deposited over the dielectric layer 1106 andmetal conductors 1108, and then planarized using a CMP operation. FIG.12 shows the resulting structure.

In FIG. 13, a frontside handle wafer 1300 is attached to the oxide layer1200 above the last metal layer, and the backside temporary carrierwafer 900 is removed. The handle wafer 1300 may be attached using, forexample, low temperature oxide-to-oxide bonding.

FIG. 14 shows the image sensor wafer flipped again for further backsideprocessing. The frontside handle wafer 1300 serves as a substrate,providing support for the structure for the further backside processing.This further processing may include, for example, forming CFAs on thebackside surface of the oxide layer 800 for respective ones of the pixelarrays. Generally, each of the pixel arrays of the image sensor waferhas a corresponding CFA which includes color filter elements that arearranged over respective photosensitive elements 1100 of the sensorlayer. Microlenses may also be formed over respective color filterelements of the CFAs. The CFAs and their associated microlenses are notshown in the figure, but can be arranged in a well-known conventionalmanner.

The color filter elements and associated microlenses are aligned withthe alignment marks 300, so as to provide accurate alignment between thephotodiodes of the sensor layer and the corresponding color filterelements of the CFA.

The resulting processed image sensor wafer is then diced into aplurality of image sensors configured for backside illumination, one ofwhich is the image sensor 14 in digital camera 10. The wafer dicingoperation will be described in greater detail below in conjunction withFIG. 15. The handle wafer 1300 in this embodiment is not removed priorto dicing, but instead serves as a permanent handle wafer, portions ofwhich remain part of respective ones of the image sensors that areseparated from one another in the dicing operation.

In an alternative embodiment, a second temporary carrier wafer may beused in place of the handle wafer 1300. The second temporary carrierwafer, like the first temporary carrier wafer 900, may be attached usingepoxy or another suitable adhesive. After attachment of the secondtemporary carrier wafer, a transparent cover sheet comprisingtransparent covers overlying respective ones of the CFAs may be attachedto the backside surface of the image sensor wafer prior to removing thesecond temporary carrier wafer. Each such glass cover may comprise acentral cavity arranged over its corresponding CFA and further compriseperipheral supports secured to the backside surface of the oxide layer800 via epoxy. The transparent cover sheet may be formed of glass oranother transparent material. Such a cover sheet may be attached to thewafer as a single sheet which is divided into separate covers when theimage sensors are diced from the wafer. Further details regarding theuse of such a temporary carrier wafer and transparent cover sheet may befound in the above-cited U.S. Patent Application Kodak Docket No. 94872.However, it is to be appreciated that use of such elements andassociated processing operations is not a requirement of the presentinvention.

Other illustrative operations that may be performed in a givenembodiment of the invention include, for example, the formation ofredistribution layer (RDL) conductors, the formation of a passivationlayer, and formation of contact metallizations.

As indicated above, the processing operations illustrated in FIGS. 2through 14 are wafer level processing operations applied to an imagesensor wafer. FIG. 15 shows a plan view of an image sensor wafer 1500comprising a plurality of image sensors 1502. The image sensors 1502 areformed through wafer level processing of the image sensor wafer 1500 asdescribed in conjunction with FIGS. 2 through 14. The image sensors arethen separated from one another by dicing the wafer along dicing lines1504. A given one of the image sensors 1502 corresponds to image sensor14 in digital camera 10 of FIG. 1.

The above-described illustrative embodiments advantageously provide animproved processing arrangement for forming a backside illuminated imagesensor. For example, the process described in conjunction with FIGS. 2through 14 provides additional backside features, such as shallowbackside trenches with associated backside field isolation, passivationand well isolation implants, that substantially reduce carrierrecombination and crosstalk between adjacent photodiodes. This providesa backside illuminated image sensor that exhibits improved performancein terms of an enhanced ability to detect incident light, withoutsignificantly increasing image sensor die size or cost.

The invention has been described in detail with particular reference tocertain illustrative embodiments thereof, but it will be understood thatvariations and modifications can be effected within the scope of theinvention as set forth in the appended claims. For example, theinvention can be implemented in other types of image sensors and digitalimaging devices, using alternative materials, wafers, layers, processsteps, etc. Thus, various process parameters such as layer thicknessesand dopant concentrations described in conjunction with the illustrativeembodiments can be varied in alternative embodiments. These and otheralternative embodiments will be readily apparent to those skilled in theart.

PARTS LIST

10 digital camera

12 imaging stage

14 backside illuminated image sensor

16 processor

18 memory

20 display

22 input/output (I/O) elements

200 silicon-on-insulator (SOI) wafer

202 substrate

204 buried oxide (BOX) layer

206 sensor layer

206B sensor layer backside surface

206F sensor layer frontside surface

210 epitaxial wafer

212 substrate

214 sensor layer

220 pad oxide layer

222 pad nitride layer

300 alignment marks

400 backside trench

402 field isolation implant region

500 trench fill material

600 antireflective oxide layer

602 antireflective nitride layer

604 backside passivation implant region

700 photoresist

702 openings

704 backside well isolation implant region

800 backside oxide layer

900 backside temporary carrier wafer

1100 photosensitive elements

1102 frontside trench

1104 frontside well isolation implant region

1106 dielectric layer

1108 last metal layer conductor

1200 oxide layer

1300 frontside handle wafer

1500 image sensor wafer

1502 image sensors

1504 dicing lines

1. A wafer level processing method for forming a plurality of imagesensors each having a pixel array configured for backside illumination,the image sensors being formed utilizing an image sensor wafer, theimage sensor wafer comprising a substrate and a sensor layer formed overthe substrate, the method comprising the steps of: forming backsidetrenches in a backside surface of the sensor layer; implanting a dopantinto the sensor layer through the backside trenches so as to formbackside field isolation implant regions corresponding to the backsidetrenches; filling the backside trenches; forming at least oneantireflective layer over the filled backside trenches; and furtherprocessing the image sensor wafer to form the plurality of imagesensors.
 2. The method of claim 1 wherein the image sensor wafercomprises a silicon-on-insulator (SOI) wafer having a buried oxide layerarranged between the substrate and the sensor layer.
 3. The method ofclaim 1 wherein the image sensor wafer comprises an epitaxial waferhaving a P− sensor layer formed over a P+ substrate.
 4. The method ofclaim 1 farther comprising the steps of: forming an oxide layer over thesensor layer; forming a nitride layer over the oxide layer; formingalignment marks that extend through the oxide and nitride layers andinto the sensor layer.
 5. The method of claim 4 wherein the step offorming backside trenches in the backside surface of the sensor layerfurther comprises the step of etching the backside trenches through thenitride and oxide layers.
 6. The method of claim 1 further comprisingthe step of forming a liner oxide layer within the backside trenches. 7.The method of claim 1 wherein the step of filling the backside trenchescomprises filling the backside trenches with one of oxide andpolysilicon.
 8. The method of claim 7 wherein the step of forming atleast one antireflective layer over the filled backside trenches on thebackside surface of the sensor layer further comprises the steps of:forming an antireflective oxide layer on the backside surface of thesensor layer; and forming an antireflective nitride layer over theantireflective oxide layer.
 9. The method of claim 8 farther comprisingthe step of performing a passivation implant operation in conjunctionwith the formation of the antireflective oxide layer.
 10. The method ofclaim 8 wherein the antireflective oxide layer has a thickness ofapproximately 50 Angstroms and the antireflective nitride layer has athickness of approximately 500 Angstroms.
 11. The method of claim 1further comprising the steps of: depositing a photoresist over theantireflective layer; patterning the photoresist to form openings overthe backside trenches; and implanting a dopant through the openings toform backside well isolation implant regions corresponding to thebackside trenches.
 12. The method of claim 1 wherein the step of furtherprocessing the image sensor wafer to form the plurality of image sensorsfurther comprises the steps of: forming an oxide layer over said atleast one antireflective layer; attaching a temporary carrier wafer to abackside surface of the oxide layer; removing the substrate; formingphotosensitive elements of the pixel arrays in the sensor layer; formingfrontside trenches in a frontside surface of the sensor layer; formingfrontside field isolation implant regions corresponding to the frontsidetrenches; filling the frontside trenches; forming frontside wellisolation implant regions corresponding to the frontside trenches;forming at least one dielectric layer on the frontside surface of thesensor layer; attaching a handle wafer to a frontside surface of said atleast one dielectric layer; removing the temporary carrier wafer; andseparating the image sensor wafer into the plurality of image sensors.13. The method of claim 12 wherein said at least one dielectric layercomprises an interlayer dielectric and further comprises an intermetaldielectric separating multiple levels of metallization.
 14. An imagesensor having a pixel array configured for backside illumination,comprising: a sensor layer comprising a plurality of photosensitiveelements of the pixel array; an oxide layer adjacent a backside surfaceof the sensor layer; and at least one dielectric layer adjacent afrontside surface of the sensor layer; wherein the sensor layercomprises a plurality of backside trenches formed in the backsidesurface of the sensor layer and arranged to provide isolation betweenrespective pairs of the photosensitive elements, said backside trencheshaving corresponding backside field isolation implant regions formed inthe sensor layer.
 15. The image sensor of claim 14 farther comprising atleast one antireflective layer arranged between the oxide layer and thesensor layer.
 16. The image sensor of claim 14 wherein the sensor layerfurther comprises a plurality of frontside trenches formed in thefrontside surface of the sensor layer and arranged between respectivepairs of the photosensitive elements in alignment with correspondingones of the backside trenches, said frontside trenches havingcorresponding frontside field isolation implant regions formed in thesensor layer.
 17. The image sensor of claim 16 wherein the backsidetrenches have corresponding backside well isolation implant regionsformed in the sensor layer in alignment with the backside trenches andthe frontside trenches have corresponding frontside well isolationimplant regions formed in the sensor layer in alignment with thefrontside trenches.
 18. The image sensor of claim 14 wherein said imagesensor comprises a CMOS image sensor.
 19. A digital imaging devicecomprising: an image sensor having a pixel array configured for backsideillumination; and one or more processing elements configured to processoutputs of the image sensor to generate a digital image; wherein saidimage sensor comprises: a sensor layer comprising a plurality ofphotosensitive elements of the pixel array; an oxide layer adjacent abackside surface of the sensor layer; and at least one dielectric layeradjacent a frontside surface of the sensor layer; wherein the sensorlayer comprises a plurality of backside trenches formed in the backsidesurface of the sensor layer and arranged to provide isolation betweenrespective pairs of the photosensitive elements, said backside trencheshaving corresponding backside field isolation implant regions formed inthe sensor layer.
 20. The digital imaging device of claim 19 whereinsaid imaging device comprises a digital camera.